| 摘要 |
PURPOSE:To eliminate the need for a network, decoder, etc., and to simplify the circuit constitution by setting a binary data sequence corresponding to a half- cycle sine wave signal from parallel input terminals of a shift register, and shifting the data with the output signal of a frequency dividing circuit as a clock signal. CONSTITUTION:When 16-bit binary data is set in the shift register 6 through parallel input terminals P and 697Hz is set by a setting circuit 3, the frequency dividing circuit 2 outputs a clock signal of (697X16X2)Hz. The register 6 is put in shifting operation with this signal and a pulse signal is outputted from its output terminal Q. This signal is converted by integration 8, and further converted by an LPF5 to obtain a positive half-cycle sine wave. Simultaneously, the serial output of the register 6 is inverted 7 and inputted to the serial input terminal D of the register 6 to obtain a negative half-cycle sine wave, so that the sine wave signal of frequency set by the circuit 3 is outputted continuously and similarly thereafter. |
