发明名称 FORMING METHOD OF MULTILAYER WIRINGS
摘要 PURPOSE:To fine the size of metallic wirings by depositing Si, to which an impurity is added in high concentration, onto a wiring metallic layer as a lower layer and connecting the wiring metallic layer as the lower layer to a wiring metal as an upper layer through the Si layer. CONSTITUTION:Al 1 is deposited onto an inter-layer insulating film 6, and Si 3 in high impurity-concentration is deposited continuously onto the whole surface through a sputtering method in the same device. Si 3 is etched in width L1 and an inter-layer insulating film 5 is superposed, and a through-hole 4 in width W1, W2 is formed. Al 2 as a second layer is deposited, and a wiring in width L2 is shaped through etching. Lastly, Al 1 and 2 are alloyed with Si 3 and connected through annealing at 400-450 deg.C. According to the method, since Si 3 functions as an etching mask, Al 1 as a lower layer is not etched. Consequently, wiring width L1 and L2 can be fined without being limited by the width W1, W2 of the through-hole. In the constitution, a wiring metal and Si are mounted and can be shaped easily as deposition sources in a conventional metal depositing device or evaporating device.
申请公布号 JPS6149440(A) 申请公布日期 1986.03.11
申请号 JP19840171870 申请日期 1984.08.17
申请人 MATSUSHITA ELECTRONICS CORP 发明人 YAMAMOTO MASAHARU
分类号 H01L21/768 主分类号 H01L21/768
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