发明名称 |
XxY Bit array multiplier/accumulator circuit |
摘要 |
An XxY bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.
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申请公布号 |
US4575812(A) |
申请公布日期 |
1986.03.11 |
申请号 |
US19840615989 |
申请日期 |
1984.05.31 |
申请人 |
MOTOROLA, INC. |
发明人 |
KLOKER, KEVIN L.;CIESLAK, RONALD H. |
分类号 |
G06F7/533;G06F7/50;G06F7/506;G06F7/508;G06F7/52;G06F7/53;G06F7/544;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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