| 摘要 |
<p>PURPOSE:To reduce the cost of the titled signal generator by unifying the arithmetic processes of an output arithmetic means with the specific value set by a constant setting means and forming the speed dimensions from the count result of detection pulses of an encoder. CONSTITUTION:A speed signal generator 17 contains a CPU19, a ROM21 and a RAM23. Two counters 25 and 27, D/A converters 29 and 31, a dip switch 35, etc. are connected to the generator 17. While encoders E1 and E2 are connected to counters 25 and 27 via direction discriminating circuits 37 and 39 respectively. The switch 35 is used for input of the characteristic values of said encoders E. The CPU19 calculates a reference magnification ratio K unify the arithmetic systems of the output value based on said characteristic values. The counter 25 counts the pulses given from the encoders E, and the CPU19 forms the speed dimensions. The ratio K is multiplied by said speed dimensions, and the output voltage of a buffer amplifier 41 is controlled to a proper level via a D/A converter 19.</p> |
