发明名称 Vector processing system.
摘要 <p>The vector processing system comprises a main memory (3) for storing instructions and operands; at least one scalar register (4) accessible by each of said instructions; a plurality of vector registers (V0-V7) each having a plurality of storage locations for holding a plurality of vector elements of an ordered set of data; functional means for performing a predetermined operation for at least one set of said vector elements in at least one vector register in response to a first instruction. First storage means store the number MVL (a positive integer) of storage locations to be used in each of said vector registers. In response to a second instruction a control means transfers the content of said first storage means to either said scalar register or said main memory. The number of said vector elements are held by a second storage means and are supplied to said functional means, based upon the content MVL of said first storage means transferred to either said scalar register or said main memory and the number N (a positive integer) of vector operations specified by a third instruction. Read-out means sequentially read out said vector elements in said at least one vector register to said functional means in response to the content of said second storage means. This vector processing system is capable of setting the number of storage locations to be used in vector registers. </p>
申请公布号 EP0173040(A2) 申请公布日期 1986.03.05
申请号 EP19850108617 申请日期 1985.07.10
申请人 NEC CORPORATION 发明人 WATANABE, TADASHI C/O NEC CORPORATION
分类号 G06F17/16;G06F15/78;(IPC1-7):G06F9/38 主分类号 G06F17/16
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