| 摘要 |
An analog-to-digital converter incorporating a series arrangement (3, 4, 5, 6) of an integrating circuit (3), a comparison circuit (4), a flip-flop (5) and a gate (6), a clock pulse signal being applied to the two last-mentioned components. An output of the flip-flop (5) is fed back to the input (14) of the integrating circuit (3) to which also the signal to be converted is applied via a switchable current source circuit (15). For effecting an optimum (ideal) integration resulting in a linear conversion, the integrating circuit (3) has a construction as shown in the drawing, it being essential for the product of the value of the capacitor 9 and the resistor 10 to be substantially equal to the value of the capacitor 12 and the resistor 11. The capacitor values and the resistor values may, for example, be equal. |
