| 摘要 |
PURPOSE:To relieve the load to be inflicted on the device of the next order by constituting the titled device with a signal detection circuit, a buffer memory, an address pointer memory, a head address designation memory and a hard cue, receiving a signal string subject to time division multiplex and allowing the next order device to extract a reception signal in the unit of one signal block. CONSTITUTION:A signal detection circuit 12 detects an end signal, which is written in a buffer memory 16 to revise the content of an address pointer memory 17. Then end signal detection information 15 is outputted from the signal detection circuit 12 and the detected end signal and corresponding channel number information 20 are stacked to the hard cue 21. Further, the next order device reads periodically the hard cue 21 to read a channel number whose one signal block is finished, the head address corresponding to the said channel is read from the head address designation memory 19 to confirm the address of the buffer memory 16 in which the head signal of the signal block is stored and the signal block of the channel is read from the buffer memory 16. |
