| 摘要 |
PURPOSE:To reduce a gate length by sequentially laminating the desired conductive type high conductive layer, a low conductive layer and a high conductive layer in this order in the thicknesswise direction of a wafer, using the surfaces of the both high conductive layers as source and drain, and forming the opposite conductive type region on the sides of the high and low conductive type layers as a gate. CONSTITUTION:An ohmic electrode 15 is positively biased to an ohmic electrode 14, the electrode 15 as a drain and the electrode 14 as a source. When the electrode 13 is set to the same voltage as the electrode 14, a current flows from the drain to the source. Then, when the electrode 13 is negatively biased to the electrode 14, a depletion layer is extended from the boundary between the P type layer of the P<+> type GaAs layer 12 and a buffer layer 9, the layer 10 and the N type layer of N<+> type GaAs layer 11. The thickness of the depletion layer is mostly extended in the layer 10 of the minimum impurity density to shut off a current between the drain and the source. Thus, a short channel effect can be eliminated at a superhigh speed to obtain low wiring resistance. |
