发明名称 SORTING PROCESSOR
摘要 PURPOSE:To execute a merge operation in the time being proportional to the number of data by providing a sorting means for extracting the maximum and the minimum data from plural data, and determining a data train based on an identifier by adding and detaching to and from the sorted data. CONSTITUTION:In an initial sorting stage, an operation in a conventional sorting processing is executed, and plural strings are obtained in a buffer memory 15. Subsequently, in a merge stage, with regard to (k) pieces of strings stored in the buffer memory 15, one data of the maximum or the minimum is outputted as a result of merge by using a sorting circuit 7. Next, the next minimum or maximum data is fetched from the string in which the data outputted as a result of merge has been contained, inputted to the sorting circuit 7, joined together with the remaining data of (k)-1 pieces, and the extracting operation is executed repeatedly plural times. A bank address is cut from (k) pieces of data to which the bank address has been given, and given to an address generating circuit 13, and a data address to be read out in the next time to the buffer memory 15 is determined.
申请公布号 JPS6142031(A) 申请公布日期 1986.02.28
申请号 JP19840163519 申请日期 1984.08.03
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SATO TETSUJI;TSUDA NOBUO;KAWADA TADAMICHI
分类号 G06F7/24;G06F7/32 主分类号 G06F7/24
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