| 摘要 |
PURPOSE:To cancel malfunction due to the response lag of a subscanning mechanism by delaying pulses of a motor for subscanning mechanism drive by twice the period of a start pulse. CONSTITUTION:Between binary-coding circuit 2 and line memory group 4, new line memory group 3 including four line memories B1-B4 and their control circuit R/W is provided. Then, when picture signals from circuit 2 are written in those memories cyclically and sucessively, lines are changed at the timing obtained by delaying driving pulse MP of motor 6 for subscanning mechanism drive by twice the period of a start pulse, and when they are read out of those memories, lines are changed at the timing of pulse MP and its read and write are performed independently. Therefore, reading and writing starting at a halfway point of one line are eliminated and malfunction due to the response lag of the pulse motor, etc., can be raveled. |
