Complementary bi-mis gate circuit.

摘要

A complementary Bi-MIS gate circuit having two CMIS circuits each consisting of a PMIS transistor (P,, P2) connected to a high potential source, an NMIS transistor (N,, N2) connected to a low potential source, and an impedance element (R,, R2) inserted between the PMIS and NMIS transistors (P1, P2, N1, Nz) and a load driving inverter consisting of a vertically structured pull-up bipolar transistor (T,) and a vertically structured pull-down bipolar transistor (T,), these bipolar transistors (T,, T2) being connected in series. The base terminals of the pull-up and pull-down bipolar transistors (T,, T2) are connected to a high level end of the impedance element (R1) in one CMIS circuit and to a low level end of the impedance element (R2) in the other CMIS circuit respectively The input signal of the complementary Bi-MIS gate circuit is fed to the gate terminals of all the PMIS and NMIS transistors (P1, P2, N,. N2) and the output signal of the gate circuit is taken from the connecting point of the pull-up and pull-down bipolar transistors (T,, T2). The impedance element (R,, R2) in each CMIS circuit works to reduce a rush current which flows through the CMIS circuit and to remove a rush current which tends to flow through the pull-up and pull-down bipolar transistors (T1, T2) when the input signal changes its level from low to high or from high to low.