| 摘要 |
In a sum-of-products multiplier, such as is used in a digital filter, it is desired to be able to produce the sum of a number of independent multiplications of binary numbers each representing a signal value, i.e. <IMAGE> where v is the sum of products, uj are the inputs and aj are weighting coefficients by which the inputs are to be multiplied. A known multiplier functions on the basis of precomputed weighting coefficients stored in a memory but this needs a very large memory and the pre-computation needs a complex device with many adders. In the novel device the memory is split into two (or more) sub-memories between which the pre-computed coefficients are shared. The coefficients are extracted for use if an input digit is 1 (but not if it is 0) and are passed via an adder where they will add to the coefficients from the other sub-memory and passed to an accumulator/shifter whose content is shifted after each digit place and whose output is the sum of products. There are also other modes of operation which allow the coefficients to be updated while the multiplier is performing computations. The overall saving in memory is considerable, and the computation device for the coefficient is much smaller than in the known devices. Thus the apparent extra complexity of the adder is more than counter-balanced by the reduced size of memory and other circuitry needed.
|
