<p>: The present invention relates to an input buffer circuit. The circuit is comprised of a source follower circuit which includes first and second FETs of identical conductivity type connected in series. A gate of the first FET is connected to an input circuit for receiving an input signal. The buffer circuit further includes a FET inverter circuit which receives an output of the source follower circuit which is derived from between the first and second FETs. The transition logic level of the source follower circuit is controlled by a voltage which is applied to a gate of the second FET in the source follower circuit.</p>
