CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors

摘要

An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.