| 摘要 |
PURPOSE:To perform synchronization to LSI to be inspected having a high speed clock cycle, by setting the comparison result of the data from LSI to be inspected and an expected value in a flag form and discriminating whether synchronization was completed on the basis of said set state. CONSTITUTION:The signal value from LSI to be inspected is at first compared with a preset expected value in a state 4 and, when both values coincide, FLG is set to 1 and, when do not coincide, FLG to discriminate whether FLG is 1 or 0 in a state 5. When FLG is 1, the content of a program counter is made incremental in a state 8 and FLG is cleared to complete synchronization. Next, when FLG is 0, the data thereof is stored in the program counter in a state 6 and FLG is cleared while a dummy cycle is formed in a state 7 to prevent the detection of synchronization from becoming impossible. |
