发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To facilitate easy detection of a fault by using an AC OR circuit and an AC AND circuit and having mutual connection between the output terminals and input terminals of both circuits. CONSTITUTION:A signal receiver 10 receives the signal waves sent from a make- busy equipment by a power receiver 16, etc. and delivers a limit speed signal A having discriminated contents. A speed comparator 11 compares the speed data given from a speed sensor 17 for a speed generator, etc. with the signal A. For an output B, the pulse control of about 500Hz is delivered in a driving mode at a limit speed or less. Then a DC signal is delivered in case the speed exceeds the limit level. A memory circuit 13 consists of an AC OR3 and an AC AND4, and the truth values among terminals A and B and an output P are shown in a table.
申请公布号 JPS6136802(A) 申请公布日期 1986.02.21
申请号 JP19840158251 申请日期 1984.07.27
申请人 HITACHI LTD 发明人 OMURA SUMIO
分类号 B60L3/08;G05B9/02;H03K3/037;H03K19/007 主分类号 B60L3/08
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