| 摘要 |
This method consists in using a frame locking word decoder 24 connected to the outputs of a shift register 21, 22 which receives at the input 1 the received data train and which has its rate controlled by a clock signal from a selection of the periods of the data train rate signal reproducing a periodic pattern formed by relative positions of bits over the duration of a frame, at least some of which are distributed in accordance with the distribution of the bits of a locking word in a frame and which form groups of the same size regularly distributed over the duration of a frame. This clock signal is generated in the device represented by a divider by twenty or twenty-one 23 which makes the periodic phase jump of the value of a data train rate period as long as the locking word is not recognised by the decoder. The shift register is made in two parallel parts 21, 22 which are regulated by the phase-shifted versions of the clock signal, the part 22 ensuring the parallel updating of the part 21 at each phase jump of the clock signal. <IMAGE>
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