| 摘要 |
PURPOSE:To prevent a data error due to a clock break which occurs at the time of selecting and switching the system by adding a synchronizing circuit composed of a clock selecting circuit and system selecting signal synchronizing circuit. CONSTITUTION:A synchronizing circuit, composed of a clock selecting circuit SEL2 and an FF as a system selecting signal synchronizing circuit,is added. The synchronizing circuit FF receives a nonsynchronous system selecting signal S at a D input, and fetches said signal S at the fall of a clock terminal CK. An output C2 of a selecting circuit SEL2, namely, a clock C0 or C1, is supplied to the clock terminal CK. This relation is so controlled that said output C2 will be opposite to an output C of a system selecting circuit SEL1. Thus, a synchronous system selecting signal S', which is synchronized at the fall of a clock C2, is outputted from a Q output of the synchronizing circuit FF, and drives the circuit SEL1. In such a manner, a data error due to a clock break, which occurs at the time of system selection switching, can be prevented. |
