| 摘要 |
PURPOSE:To make it possible to determine whether or not wiring between two chips is made wall, by providing with circuits each selecting one of an operating signal and a testing signal on a first semiconductor chip, and an AND-gate into which a group of outputs of the selecting circuits are inputted and wiring for connecting the output of the AND-gate with a detecting terminal of the first chip on a second semiconductor chip. CONSTITUTION:On a chip A, each selecting circuit 1 is provided at respective from stages of output buffers A1-An for respective connections. The LSI becomes a normal operating mode when the control signal CNIL is ''0'' and a testing mode when the signal CNTL is ''1''. On a chip B, an n-input AND-gate 2 is provided at the back of input-buffers B1-Bn for the respective connections. The output of the AND-gate 2 is connected to the detecting terminal 6 through an output-buffer 3, a detecting connection 4 and an input-buffer 5 of the chip A. The number of (n) of the testing terminals and one detecting terminal of the chip A are shared with external terminals. Thus to test wiring between the chips can be attained by adding only one control terminal. |
