| 摘要 |
PURPOSE:To reduce the junction capacitance by lessening the variation in threshold value, and to prevent the flow of through-current at the time of the turn- ON of the power source by a method wherein a region incuding the readout transistor of a memory cell is formed in a well and then impressed with well biases. CONSTITUTION:Memory nodes 13 are provided in the surface of the P-well 12 formed in an N type substrate 11, and a thermal oxide film 14 is formed. Word lines 15 and a capacitor-opposited electrode 16 are provided at required positions of the film 14, an oxide film 17 being formed, and a bit film 18 being then provided. Well biases are impressed on the P-well 12 by the use of a negative voltage generation circuit. Restriction of the part of well bias impressing to the memory cell and inhibition of substrate bias impressing to peripheral circuits such as a sense amplifier and an output buffer prevent the through-curent at the time of the turn-ON of the power source. |
