发明名称 |
Buffer circuit for random access memory. |
摘要 |
<p>A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.</p> |
申请公布号 |
EP0171518(A2) |
申请公布日期 |
1986.02.19 |
申请号 |
EP19850105724 |
申请日期 |
1985.05.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHUNG, PAUL WING-SHING;MATICK, RICHARD EDWARD;LING, DANIEL TAJEN |
分类号 |
G11C11/401;G06F12/00;G11C7/10;G11C11/4093 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|