发明名称 |
Timing apparatus for non-volatile MOS RAM |
摘要 |
A non-volatile memory and in particular the timing apparatus for generating sequence of signals needed for storing and recalling data is described. The memory cell employs an E2 cell which is coupled to a bistable (static) RAM cell. "State machine" logic is employed to obtain the proper sequence of signals needed for storing and recalling.
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申请公布号 |
US4571709(A) |
申请公布日期 |
1986.02.18 |
申请号 |
US19830462190 |
申请日期 |
1983.01.31 |
申请人 |
INTEL CORPORATION |
发明人 |
SKUPNJAK, JOSEPH A.;LEE, DOUGLAS J.;BECKER, NEIL J. |
分类号 |
G11C14/00;G11C7/22;G11C16/32;(IPC1-7):G11C7/00 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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