| 摘要 |
<p>A SYNCHRONISING ARRANGEMENT: Fig. 1 A t.d.m. signal of a high order with a block-form frame code word is distributed between a plurality (four) of channels in a demultiplexer and is supplied to inputs ( 1 to 4) of the synchronising arrangement. A data transmission section of the synchronising arrangement contains stores (5,6,8) and a channel distributor (7). The channel distributor (7) is controlled by means of the first store (5) via a control section comprising a decoder (13), stores (14,15), and a coder (16). A logic-linking arrangement (17) and a frame counter (18) permit resynchronisation only when the frame code word has failed to appear four times. The synchronising arrangement facilitates high-speed synchronisation at bit rates of 140 Mbit/s and 565 Mbit/s, and also permits integrated circuit construction in ECL technology.</p> |
