MEMORY CLEAR CONTROLLING SYSTEM

摘要

PURPOSE:To shorten a necessary time of a memory clear by executing a control so that write is executed simultaneously to plural memory element groups, when executing the memory clear of a storage device. CONSTITUTION:When executing a memory clear operation of a CPU 1, a memory clear state signal MCL is logic 1, and memory element group designating signals CSO, CS1 both become logic 1. Accordingly, when a memory block designating signal BCO is logic 1, a timing signal WTM 101 is supplied to a memory element group 101, and simultaneously, a timing signal WTM102 is supplied to a memory element group 102. Also, when a memory block designating signal BS1 is logic 1, a timing signal WTM201 is supplied to a memory element group 201, and simultaneously, a timing signal 202 is supplied to a memory element group 202. In such a way, the timing signal is always supplied simultaneously to two memory element groups, by which a necessary time of the memory clear operation can be shortened.