| 摘要 |
PURPOSE:To execute in a short time a priority selection of an interruption processing request from an I/O, and also to reduce an interruption processing signal applied to a processing circuit by executing the priority selection of an interruption processing between adaptors of plural I/Os. CONSTITUTION:Adaptors #0-#3 have a circuit for controlling an I/O, and a priority order of an interruption, etc. is determined by this circuit. An interrupting signal is stored in an interruption register IR01, and its output is provided to an OR gate OR01 and OR is executed. This result is outputted to a common part 1 and an AND gate A01, and the common part 1 outputs an interruption receiving signal to the adaptors #0-#3. As a result, the adaptors #0-#3 execute a priority selection of an interruption processing by its signal and reply automatically in response to an interruption reception of a common processing circuit successively from an interruption of a high level. In this way, the priority selection of the interruption processing request from the I/O can be executed in a short time, and an interruption processing signal applied to the processing circuit can be reduced. |
