发明名称 LOGICAL DIVISION SYSTEM
摘要 PURPOSE:To reduce the output of a gate array by dividing the 1st logical circuit to be sliced into two gate arrays and selecting and outputting the output of a required logical circuit out of the 2nd logical circuits formed in respective gate arrays by a multiplexer. CONSTITUTION:A hardware 8 to be sliced is divided into two gate arrays, hardwares 9 each of which is formed as a gate array by incorporating hard wares 4, 5 having originally independent functions each other are added to respective gate arrays and any one of the hardwares 4, 5 is selected and outputted by the multiplexer 10 on the basis of the signal obtained from a switch 12. Consequently, the gate arrays 8, 9 can be combined as one gate array.
申请公布号 JPS6133536(A) 申请公布日期 1986.02.17
申请号 JP19840154018 申请日期 1984.07.26
申请人 TOSHIBA CORP 发明人 IGARASHI SATORU;AOYANAGI KEIZO
分类号 G06F7/00;H03K19/173 主分类号 G06F7/00
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