发明名称
摘要 PURPOSE:To simplify wiring layouts, reduce chip areas and prevent the decrease in signal effective value by connecting the source contacts of MOS elements in bit line selectors to the common source contacts of FF amplifiers thereby reducing contact buses. CONSTITUTION:When the common source nodal point 113 of MOS type elements Q110-Q112 by which the antilogarithms or complementary numbers of specific addresses are applied to the gates of respective bit line selectors 2a... are connected to the common nodal point 103... which are grounded and connected via the MOS element Q107 of FFs 1a... amplifying the signals of bit lines 101..., the ground buses connecting the nodal points 113 and the ground can be reduced. This makes it possible to increase the degree of freedom, to simplify wiring layouts, and to reduce chip areas. There is no effect of electrostatic capacity and the decrease in signal effective value is prevented by the reduction in the ground buses.
申请公布号 JPS615234(B2) 申请公布日期 1986.02.17
申请号 JP19800059751 申请日期 1980.05.06
申请人 NIPPON ELECTRIC CO 发明人 TADA KAZUHIRO;IKEDA HIROAKI
分类号 G11C11/408;G11C5/02 主分类号 G11C11/408
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