发明名称
摘要 PURPOSE:To improve the stability of frequency, by providing a means to compensate the suppression of modulation caused by a PLL. CONSTITUTION:The digital adder 28 adds the output of the A/D converter 26 to the frequency setting signal 303 to produce a setting frequency value obtained by adding the frequency equivalent to an amount to be added to the FM modulation to the set frequency by the frquency setting signal 303, and then adds the frequency value to the 1/N variable divider 23. An FM modulation of the frequency less than the cut-off frequency of the closed loop transmission property of a PLL is mainly carried out through the low pass filter 27, A/D converter 26, digital adder 28, 1/N variable divider 23 and PLL. While an FM modulation is carried out for the frequency higher than the cut-off frequency by the signal applied directly to the frequency/voltage variable oscillator 21.
申请公布号 JPS615285(B2) 申请公布日期 1986.02.17
申请号 JP19800021104 申请日期 1980.02.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IIDA TOMOYA
分类号 H03C3/00;H03C3/09 主分类号 H03C3/00
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