| 摘要 |
<p>The processor includes respective paths (1,2) for receiving first f(t) and second g(t) input waveforms, a respective delta A-D converter (3,4) being provided in each path for convert signals in the respective path to a digital version having a delta modulation format. A summing device (5) is coupled to the outputs of the two paths.A pair of integrators (6,7) is coupled either in the first path, or the second path, or both paths, or the output of the summer, or the first path and the output of the summer, or the second path and the output of the summer. - The convolution function is provided at the output of the summer when the integrators in one or both paths and at the output of one integrator when the integrators are coupled otherwise. Pref. each delta A-D converter is a one-bit converter and includes an amplitude comparator (9) a D-type flip-flop (10), a clock source (8) and an analogue integrator (11).</p> |
