| 摘要 |
PURPOSE:To prevent a latch-up generated in a C-MOS circuit at a time when excess voltage is applied by connecting a Zener diode between an input/output terminal for the C-MOS circuit connected to a terminal pin and a power supply. CONSTITUTION:When Zener diodes D1, D2 are connected between an input terminal IN and a power supply VSS, no latch-up is generated even when excess positive voltage is applied to the input terminal IN. That is, the Zener diodes D1, D2 are broken down before a P-N junction between layers 28 and 10 is broken down at that time, and excess positive voltage is dropped to the power supply VSS (a ground). Accordingly, since the P-N junction between the layers 28 and 10 is not broken down, the potential rise of a substrate 10, the forward bias of a P-N junction between layers 14 and 10 and the ON of a transistor Qa, the latch-up of C-MOS inverters Q1, Q2, are not generated. |
