发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To increase the operating margin at the time of transition by a method wherein required terminals symmetric in a circuit meaning are connected to each word line by two-division of the word line arranged in a memory array and connected to each memory. CONSTITUTION:The word line is two-divided into W1 and W2: a current stand- by line IST is so arranged as to pass through the center of a memory cell, and the word lines W1 and W2 are arranged in parallel with the current stand-by line IST and in symmetry across this line. Then, the anode side terminal of the first layer Schottky barrier diode SBD1 and SBD2 are connected to the second layer word lines W1 and W2 through-holes TH1 and TH2, respectively. One-ends of diffused resistors r2 and r1 are brought into contact with the aluminum electrode (first layer) of the diodes SBD1 and SBD2 via contact holes CH1 and CH2, respectively, and the other ends of the resistors r2 and r1 are joined to the base regions B1 and B2 of transistors Q1 and Q2 via P type semiconductor region.
申请公布号 JPS6132465(A) 申请公布日期 1986.02.15
申请号 JP19840152875 申请日期 1984.07.25
申请人 HITACHI LTD 发明人 MITAMURA ICHIRO;UCHIYAMA TAKEO;KITSUKAWA GORO
分类号 G11C11/413;H01L21/8222;H01L21/8229;H01L27/082;H01L27/10;H01L27/102 主分类号 G11C11/413
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