发明名称 FORMATION OF MULTILAYER INTERCONNECTION STRUCTURE
摘要 PURPOSE:To prevent the generation of cracks in an interlayer insulating film without reducing the effect of the flattening of the interlayer insulating film by ratching only the interlayer insulating film only by desired film thickness without etching a conductor for an upper layer wiring. CONSTITUTION:A pattern for a conductor 2 for a lower layer wiring is formed onto a silicon substrate 1 to which a transistor is shaped previously, an interlayer insulating film 3 is attached onto the whole surface of the upper section of the pattern and flattened, and a pattern for a conductor 4 for an upper layer wir ing is shaped. The conductor 4 for the upper layer wiring is not etched, and the interlayer insulating film 3 section except a section just under the conductor 4 for the upper layer wiring is etched through a dry etching method by a gas such as CF4 gas. A passivation film 5 is attached onto the whole surfaces of the interlayer insulating film 3 and the upper-layer wiring conductor 4. Accordingly, only disired film thickness is etched, and the film thickness of the interlayer insulating film is reduced, thus preventing the generation of cracks, then obviating the lowering of the effect of the flattening of the interlayer insulating film 3.
申请公布号 JPS6132555(A) 申请公布日期 1986.02.15
申请号 JP19840154424 申请日期 1984.07.25
申请人 SUMITOMO ELECTRIC IND LTD 发明人 HORI MINORU;IDA JIRO;KINOMURA TADASHI
分类号 H01L21/768;H01L23/522 主分类号 H01L21/768
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