| 摘要 |
PURPOSE:To avoid a fault of a conciliation circuit from going to the entire processing system-down by decentralizing the conciliation circuit to each module. CONSTITUTION:Supposing that a module A at a time t1 and a module B at a time t2 raise a data transfer request using a bus 10 to other modules, a signal BR is made significant in response to a bus clock BCLK incoming next to the request. In this case, the module A monitors the BR line of a module having higher priority than that of the own module and when no bus request is given from other modules with high priority, the step transits to the data transfer processing. When the modules A, B offer a transfer request at times t3, t4, the module B does not monitor the BR line of the module A and becomes a bus master (in this case, the B has higher priority than the A). |
