| 摘要 |
PURPOSE:To improve the excution speed of the whole device by analysing a command given to a peripheral device and providing the timing controlling means, which pre-outputs a control signal given to the peripheral device. CONSTITUTION:When a CPU 1 writes a command (READ) to the peripheral device 4, the peripheral device 4 prepares data, asserts a DMA, REQ and data is added to a timing controlling circuit 5. At the time that the CPU 1 writes a command to the peripheral device 4, the next action of the peripheral device 4, such as read or write data is accumulated in a FF 1. In the peripheral device 4, when the DMA, REQ is asserted, the signal is added and set to FF2, FF3 through an inverter. At the same time, requests is outputted from the FF3 to a DMAC2 immediately and a DMA, ACK signal or the like are asserted to the peripheral device 4 from the output of the FF2 when a DMA bus cycle starts and a OWN (reverse) is asserted. |
