| 摘要 |
<p>PURPOSE:To select plural modulo registers and to perform complicated pulse width modulation by providing a multiplexer provided with the second binary counter and an address decoder CONSTITUTION:07, 10- are set to first modulo register 26, the second modulo register 27,- through a data bus 23 of a timer circuit. Addresses of these registers 26, 27- are discriminated by the second binary counter 29 and an address decoder 30 of a multiplexer 31, and a switching signal is applied to the multiplexer 31 to select registers 26, 27-, and values in registers are applied to a comparator 22. The output of the first binary counter 21 is inputted to the comparator 22, and the counter 29 is connected to one end of the comparator 22. When the counter 21 is incremented, the comparator 22 supplies a coincidence signal to the counter 29 and an MS-type FF24 through a coincidence signal line 32, and a timer signal is outputted from a timer output terminal 25, thus performing complicated pulse width modulation.</p> |
