| 摘要 |
PURPOSE:To attain sequential vertification the content of operation by a program of an operation processor by providing a test mode latch in the operation processor and not handling a command from a control processor as a command at the normal mode. CONSTITUTION:A command issued from the control processor 1 is latched to a command register 26 in the timing of a strobe signal from the control processor 1 via an interface line 2 (=21). When a diagnostic instruction of test mode set/ reset is issued from an instruction processing section 7 through a line 6, an FF30 is set/reset by the control section 25. When the mode latch 30 is set, an AND circuit 28 is set, an AND circuit 29 is turned off and no trigger pulse on an interface line 22 (=2) is given to the control section 25, then the command from the processor 1 is not given to the control section 25, an external interruption is issued to the instruction processing section directly through the AND circuit 28 and the interface 4 so as to attain interruption processing. |
