MASTER SLICE SEMICONDUCTOR DEVICE

摘要

A master slice semiconductor device comprising a plurality of basic cell arrays and a plurality of flip-flop cell arrays. The basic cell and flip-flop cell arrays are interconnected by strip-like diffused resistor regions with metal conductors via contact windows formed in an insulation layer on a bulk. The basic cell arrays, the flip-flop cell arrays, and the diffused resistor regions are buried in the bulk in advance. The diffused resistor regions are located in empty regions where lands, composing the basic cell and flip-flop cell arrays, are not formed in the bulk.