| 摘要 |
PURPOSE:To attain the wide-range following-up capacity and the stable clock reproducing operation by extracting clock information from a section preceding a reproduced data signal in a phase synchronizing loop nd switching operations of two loops after leading-in in a frequency synchronizing loop. CONSTITUTION:The reproduced signal of digized sounds, which are different in pulse width interval, of an input terminal 5 is delayed by delay lines 6 and 7, and a gate signal of the edge front part is generated by a gate 10 and an inverter 9, and a gate signal of the edge rear part is generated by a gate 11, and ANDs between them and the output reproduced clock signal of a VCO24 are operated and are added analogically. Meanwhile, the phase of a horizontal synchronizing signal of a terminal 17 is compared with that of the output of a frequency divider 25 of the reproduced clock signal by a phase comparing circuit 18. and the error output is impressed to a sampled and hold circuit 21 through an LPF19, and this output passed through the circuit 21 when a digital sound signal does not exist, but a sampling pulse which holds the digital audio signal is impressed from a terminal 20 when the digital sound signal exists. The output of the circuit 21 is added to the error signal of the phase synchronizing loop through a resistance 23 and is inputted to the voltage control input terminal of the VCO24. |
