| 摘要 |
An analog-to-digital converter circuit is disclosed employing a plurality of comparators each having the same reference voltage input. At each comparator stage plus and minus binary "bit weights" are developed. Selection of either the positive or negative bit weights at a stage allows a binary fraction to be added or subtracted. The number of comparator stages need only equal the number of desired digit positions in the output instead of having one comparator for each quantizing level. The comparator stages operate in a "wave" or "pipeline" manner under the control of a plurality of high speed wave forms so that each stage decodes its respective binary digit for one analog sample while the other stages are decoding their respective binary digits of other analog samples.
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