| 摘要 |
A memory circuit is disclosed having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines such that each cell is uniquely coupled between a pair of word lines and a pair of bit lines. A sensing circuit is coupled to each pair of bit lines for determining the state of a selected cell. A column decode circuit is coupled to each pair of bit lines for selecting that pair of bit lines. A read current source is coupled between the bit lines and a voltage source for sinking a read current through the bit lines. A logic selectable write current source is coupled between the bit lines and the voltage source for sinking a write current when writing the memory cells for charging and discharging diffusion capacitance within the selected memory cell. Current flows through the logic selectable write current source only during the write mode.
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