| 摘要 |
PURPOSE:To reduce restriction of output pulse width of an edge detecting circuit by using a phase comparator that compares phase of output of an input signal edge detecting circuit and output of a clock edge detecting circuit. CONSTITUTION:The edge detecting circuit 1 detects edge of rise and fall of input signals and gives detected pulse D to a phase comparator 5. The comparator 5 generates pulse K of pulse width that changes between 0-1 clock and pulse L of 1/2 clock width according to phase difference between clock C from VCO3 and detected pulse D. An LPF2 integrates pulses K, L and controls the VCO3 by the output. Thus, pulse of the clock C is changed and phase locked loop with the input signal I is realized. Thus, it becomes not necessary to make output pulse width of the edge detector 1/2 clock accurately, and restriction can be lowered. |
