| 摘要 |
<p>PURPOSE:To reduce the operating time of the titled circuit by generating a differentiated pulse signal of an input signal synchronously with a referenced clock signal so as to control the change point of time of the clock signal for operating a logical circuit being an output of a frequency division circuit. CONSTITUTION:A referenced clock signal 6 is frequency-divided by a J-KFF9 and inputted to a logical circuit 1 as a clock signal 7. On the other hand, the input signal 10 in synchronizing with the signal 6 is delayed by one clock by a D-FF11 and inputted to the circuit 1. A differentiation pulse signal 13 of the signal 10 is generated by a NAND gate 12 at the same time and inputted to a J terminal of the FF9. When the signal 10 is changed by the trailing edge of the signal 7, a waveform where the leading edge of the signal 7 is delayed by one cycle's share of the referenced signal 6 is obtained and when the signal is changed at the leading edge, the signal 7 is outputted while not being modified. As a result, the signal 14 inputted to the circuit 1 is detected in terms of operation in synchronizing with the signal 7. Thus, the operating time is reduced.</p> |
