| 摘要 |
PURPOSE:To speed up the transfer speed of data by multiplexing a bus connected to a common memory in a cycle shorter than one instruction cycle of a microprocessing unit to bring the time shared by one unit into <=1 instruction cycle. CONSTITUTION:MPU interface circuits 3, 4 are connected to the common memory 1 by a common memory bus 3 and MPU-A6, MPU-B7 and local memories 8, 9 are connected to the circuits 3, 4 via a local bus. Further, a multiple access control circuit 2 is connected to the interface circuits 3, 4. In this system, the MPU-A6, MPU-B7 transmit/receive data with the memories 8, 9 via buses 18, 19 normally. In accessing the memory 1, the control circuit 2 controls the interface cicuits 3, 4 multiplexes the common memory bus 3 in a time shorter than one instruction cycle to reduce the time shared by the MPU-A6 or the MPU-B7. |
