CLOCK SYNCHRONIZATION SIGNAL GENERATING CIRCUIT

摘要

A clock synchronization signal generating circuit includes a clock synchronizing circuit having a scale variable counter for counting a source clock signal from a source clock generator and a control circuit for controlling the scale of counter responsive to the phase difference between an input clock signal supplied from a digital operation system and an output signal from the scale variable counter, and a clock circuit including a counter for counting in n-scale mode a source clock signal from the source clock generator. The scale variable counter is selectively set to (n-1)-, n- or (n+1)-scale mode responsive to the control signal from the control circuit to generate an output signal which is clock-synchronized with the input clock signal.