| 摘要 |
PURPOSE:To perform detail analysis at high speed by decoding control information and performing the analysis by operating a circuit block by the output of a decoder after information required for the analysis of the circuit block is supplied from the outside when the circuit block is set at an operating state based on prescribed analytic sequence. CONSTITUTION:When a test mode signal MBT becomes a level '1', and the analysis is started, and a signal TEN1 generated by a sequence control signal TEN becomes a level '0', external data supported on a data pin 13 is fetched in an internal bus 5 via an I/O buffer 11. Next, when the signal TEN1 becomes the level '1', a mask signal becomes the level '0', and a mask circuit 37 becomes valid, and furthermore, when an enable signal in a TFF circuit 19 becomes the level '0', the control information set on a micro enable signal generation circuit MIR33 is decoded by a micro decoder 35, thereby, the analysis can be performed by operating macro blocks 1 and 3 by using the output of the decoder. |
