| 摘要 |
<p>Lower contact and interconnect metallization series resistance on semiconductor devices is achieved while avoiding the material and process incompatibility problems of the prior art by utilizing a composite metallization (42, 44, 49) structure employing two superposed intermetallic layers (44, 49) of different properties. The first intermetallic (44) is chosen for high conductivity and compatibility with the device interfaces. The second intermetallic (49) functions as a conductive protective "cap" and is chosen for conductivity and compatibility with subsequent process steps. The two intermetallics (44, 49) must also be compatible. For silicon devices the preferred first and second intermetallics are respectively, silicon rich titanium silicide and titanium nitride, but other materials are also useful. Polycrystalline silicon (42) is desirable for a base layer under the first intermetallic (44) in certain device structures such as MOS gates. The composite metallization is prepared by a lift-off technique.</p> |
