| 摘要 |
<p>A semiconductor memory device includes a first row decoder (10) and memory cells M11 to MNL. The first row decoder (10) receives the row address signal from an input buffer (16) and a specific row of a matrix array of memory cells M11 to MNL. The memory device further includes a second row decoder (14), a refresh address generator (18), a timing controller (30) and switching circuits (SA1 to SAN, SB1 to SBN). The second row decoder (14) selects a specific row of the matrix array according to a refresh address derived from the refresh address generator (18). The output terminals of the first and second row decoders (10, 14), are connected to the memory cells (M11 to MNL) through groups of switching circuits (SA1 to SAN, SB1 to SBN). The timing controller (30) selectively renders conductive either the switching circuit group (SA1 to SAN) or SB1 to SBN).</p> |
