Multiple instruction dispatch mechanism.

摘要

A data processing system is described which includes a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction, when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set. Similarly, an instruction is delayed if that instruction will set a bit in the condition register which is still being accessed by a previous instruction.