| 摘要 |
PURPOSE:To obtain a speedy and efficient binary/decimal added result parity predicting circuit by collecting the contents of the binary/decimal added result parity predicting circuit on one circuit when there is no carry, and if carry exists, correcting the contents of said circuit. CONSTITUTION:The binary/decimal added result parity predicting circuit (IBDPP)8 predicts a binary/decimal added result parity to be obtained when there is no carry from a carry foreseeing circuit (CLA)9. A binary/decimal added result parity inversion predicting circuit (BDPIP)10 inverts the output of the IBDPP8 when the carry of the CLA9 exists. Namely, the output of the IBDPP8 is corrected by a circuit 11 for calculating P=A exclusive OR B.ExtC on the basis of the carry from the CLA9 and the output of the BDPIP10 to obtain the final binary/decimal added result parity predicting signal. Provided that P is a parity in each byte, A is the IBDPP, B is the BDPIP, and ExtC is a circuit for forming carry in each data 1/2 bytes. |
