| 摘要 |
PURPOSE:To shorten the waiting time caused by interlocking by providing a means to deliver an interlock command and the interlock area information, a means to decode the command and a means to store the interlock area information to each of plural processors. CONSTITUTION:A central processing unit 2 and an input/output controller 3 are connected to a main memory 1 via a common bus. Microprogram control parts 2-1 and 3-1 are controlled by the microprograms stored in control memory parts 2-2 and 3-2 and then control the unit 2 and the controller 3 respectively. Decoding circuits 2-8 and 3-8 monitor command buses and also decode them. Thus the data on a data bus are fetched by registers 2-7 and 3-7 when an interlock request is detected. |
